Vivek,

   Simulating ADC dynamic performance is non-trivial. The
results are dependent on the setup of the simulation. You
will need to use the same methodology that designers use
when testing data converters on the bench. The best place
to look for information is AD/Maxim/BB. You will need to
search for information on coherent sampling. Here is one
useful link from Maxim,

        http://japan.maxim-ic.com/tools/calculators/index.cfm/calc_id/appnote3190


To summarize the issues, you need to do two things:

1) Control the time span used for the FFT data record so
    that it contains an integer number of periods of the
    clock and input signal. This will eliminate spectral
    leakage so you won't need to use windowing functions.

NOTE: Everybody uses windowing function on the testbench.
It can't be helped since it is impossible to perfectly
synchronize the clock and input. However, it can be helped
when simulating so don't do it! Windowing functions can
mask the actualy characteristics of the ADC.

2) Make the ratio of the input signal to the clock signal ,
  depend on the prime number for example. 17 periods of
  the input to 256 periods of the output. If you use even
  numbers, for example, 1MHz input for a 10MHz, sample
  rate, then the noise shows up at the harmonics of the
  beat frequency, e.g., 2MHz, 3MHz, ...
  So the SNR will be correct but the SFDR will be incorrect.
 
3) The simulation you are performing only inlcudes the
    quantitazation noise of the ADC, so you should see
    the SNR match the ideal value. I have checked this
    for 10 bit ADCs and the theory matches simulations.

                                                        Best Regards,

                                                           Art Schaldenbrand