I found a description of the difference at
http://www.asic-world.com/digital/questions.html.
Quote:What is the difference between a LATCH and a FLIP-FLOP?
- Latch is a level sensitive device and flip-flop is edge sensitive device
- Latch is sensitive to glitches on enable pin, where as flip-flop is immune to gltiches.
- Latches take less gates (also less power) to implement then flip-flops
- Latches are faster then flip-flops
They then go on to say that a flip-flop can be built from latches as follows
In this figure it seems the essential difference is a extra half clock cycle delay in the output.
But then in
http://dept-info.labri.u-bordeaux.fr/~strandh/Teaching/AMP/Common/Strandh-Tutori... they define the difference as follows ...
Quote:Both latches and flip-flops are circuit elements whose output depends not only on the current inputs, but also on previous inputs and outputs. The difference between a latch and a flip-flop is that a latch does not have a clock signal, whereas a flip-flop always does.
This is the definition I am used to.
So it seems like the terms latch and flip-flop are not used consistently by engineers.
- MM -