Hello, everyone. I am so pleased to meet you here and I hope I can get your help.

      For frequency synthesizer design, the output clock jitter will be different with the different inputs. The input with phase step, or the input frequency variant with time, which kind of input clock will introduce a larger output jitter value?
      The frequency synthesizer's input: 2MHz
                                                   Output:24MHz
      noisy input 1: 2MHz with phase step 50ns/2KHz
      noisy input 2: 1.8MHz ~ 2.2MHz (time variant)
      The PLL is composed of a 2nd-order passive filter and the 5-stages ring oscillator. The natural frequency is 40KHz(PFD input frequency is 1MHz), and the damping factor is about 0.6.
      I think the 2nd noisy input will result in the bigger output value. Because the PLL can't catch the input's time-variant phase.

       Could u tell me whether what i thought is correct? Thank you so much.

      And, if i want to get a pure output clock from a time-variant input clock, what should I do? Thank you so much.

                                     -----------YaYa------------------ ???