I am encountering convergence problem for simulating my ADC which is a 2nd order SIgma Delta Modulator.  There are two integrators and there is a quantizer involved. The quantizer output feeds back into the first integrator.

The convergence problem is seen in PSS. I am monitoring the internal nodes, namely the output of the 1st and 2nd integrators and there seems to be okay. They are not clipping towards rail.

Can someone suggest me a work around for this.


Thx

ic_engr

Ken,

Doesnt your paper on DEvice Noise Simulation of Sigma Delta Modulators and the paper "Simulating Switched-Capacitors" show examples of 2-nd order Modulators as simulated using SpectreRF. There was no mention of breaking the blocks.

Having a clock at 2MHz and being synchronous with clock I though PSS should have handeled this.

ic_engr.

Ken,

Can you seuggest me what I should do for the feedback from the quantizer to the integrator once the loop is broken.

Thx

ic_engr