Sid
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Hi Andrew,
I entered the veriloga view in a text-editor (vi), so I am not sure if there is an error in it. The code is pasted below at the end of the email - identical to Ken's THA.
The exact error I got from Cadence in the CIW is:
Begin Incremental Netlisting Apr 13 23:24:48 2005 ERROR: Netlister: unable to descend into any of the views defined in the view list: "veriloga spectre cmos_sch cmos.sch schematic ahdl" for instance I1 in cell SHA_ideal_test. Either add one of these views to: Library: boosted_swit_mar_05 Cell: SHA_ideal or modify the view list to contain an existing view. End netlisting Apr 13 23:24:48 2005
I only have 2-views for "SHA_ideal" - veriloga and symbol.
Any help would be appreciated.
Thanks, Sid
// VerilogA for boosted_swit_mar_05, SHA_ideal, veriloga // Periodic Track & Hold // // Works with SpectreRF (has no hidden state) // Almost ideal ... // Has buffered input and output (infinite input Z, zero out Z) // Exhibits no offset or distortion errors // Only nonideality is finite aperture time and very small amount of droop
`include "constants.h" `include "discipline.h"
module SHA_ideal (Pout, Nout, Pin, Nin);
electrical Pin, Nin, Pout, Nout; input Pin, Nin; output Pout, Nout; parameter real period=1 from (0:inf); parameter real tdelay=0 from [0:inf); parameter real aperture=period/100 from (0:period/2); parameter real tc=aperture/10 from (0:aperture);
integer n; real tstart, tstop; electrical hold;
analog begin
// Determine the point where the aperture begins; n = ($abstime - tdelay + aperture) / period + 0.5; tstart = n*period + tdelay - aperture; @(timer(tstart));
// Determine the time where the aperture ends; n = ($abstime - tdelay) / period + 0.0; tstop = n*period + tdelay; @(timer(tstop));
// Implement switch with effective series resistence of 1 Ohm if (($abstime > tstop - aperture) && ($abstime <= tstop)) I(hold) <+ V(hold) - V(Pin, Nin); else I(hold) <+ 1.0e-12 * V(hold);
// Implement capacitor with an effective capacitance of tc I(hold) <+ tc * ddt(V(hold));
// Buffer output V(Pout, Nout) <+ V(hold);
// Control time step tightly during aperture and loosely otherwise if (($abstime >= tstop - aperture) && ($abstime < tstop)) begin $bound_step(tc); end else begin $bound_step(period/5); end
end endmodule
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