Hi,

 I am trying to use Ken's veriloga THA (for use with SpectreRF without hidden-states). I copied the text file from:

http://www.designers-guide.org/VerilogAMS/rf-models/sh/sh.va

and created a veriloga view in cadence for a cell called sh. Then I created a symbol for sh with pins Pin, Nin, Pout and Nout.

I have never used veriloga before and do not particularly understand it. When I try to simulate a schematic with the symbol for sh instantiated in it, I get an error from Spectre that it cannot find a view to decend into sh. I made sure veriloga is listed in my "view-list". What should I do to get this to work? Do I have to "compile" the veriloga code (a wild guess)?

Also, for this SHA what do Pin, Pout, Nin and Nout represent? I was expecting the ports to be more like vin, vout and clk...

Any help will be appreciated.

Thanks,
Sid

Pin and Nin are the positive and negative input terminals. Pout and Pout are the output terminals. Vin = V(Pin,Nin) and Vout = V(Pout,Nout). If you want single sided input and output, connect Nin and Nout to ground.

There is no external clock. It samples all by itself without an externally applied clock every "period" seconds. If you want an external clock, you will need to modify the model.

-Ken

Sheldon,

     Thanks for your response. My view-list is:
"spectre cmos_sch cmos.sch schematic veriloga ahdl"
So it should be able to pick up veriloga. Not sure why it is failing. Also, my module name and the cell-view name are the same (called SHA_ideal).  Any other thing to look for or try?

   I will see if hierarchy editor helps me. I have never used it before so it may take me a while to figure it out.

Thanks,
Sid
-----------------------------------------
Ken,

   Thanks for the explanation on the THA block functionality. Hopefully I will get it to run in Cadence soon.

Thanks,
Sid

Andrew,

Thanks for the reply. My cell-name (and "module" name in the veriloga code) is "SHA_ideal" (instead of the "sh" that Ken used in his code). My view-name is "veriloga". So, I think I have that correct.

Sid

Hi Andrew,

I entered the veriloga view in a text-editor (vi), so I am not sure if there is an error in it. The code is pasted below at the end of the email - identical to Ken's THA.

The exact error I got from Cadence in the CIW is:

Begin Incremental Netlisting Apr 13 23:24:48 2005
ERROR: Netlister: unable to descend into any of the views defined in the view list: "veriloga spectre cmos_sch cmos.sch schematic ahdl" for instance I1 in cell SHA_ideal_test.
Either add one of these views to: Library: boosted_swit_mar_05 Cell: SHA_ideal or modify the view list to contain an existing view.
End netlisting Apr 13 23:24:48 2005

I only have 2-views for "SHA_ideal" - veriloga and symbol.

Any help would be appreciated.

Thanks,
Sid

// VerilogA for boosted_swit_mar_05, SHA_ideal, veriloga
// Periodic Track & Hold
//
// Works with SpectreRF (has no hidden state)
// Almost ideal ...
//    Has buffered input and output (infinite input Z, zero out Z)
//    Exhibits no offset or distortion errors
//    Only nonideality is finite aperture time and very small amount of droop

`include "constants.h"
`include "discipline.h"

module SHA_ideal (Pout, Nout, Pin, Nin);

electrical Pin, Nin, Pout, Nout;
input Pin, Nin;
output Pout, Nout;
parameter real period=1 from (0:inf);
parameter real tdelay=0 from [0:inf);
parameter real aperture=period/100 from (0:period/2);
parameter real tc=aperture/10 from (0:aperture);

integer n;
real tstart, tstop;
electrical hold;

   analog begin

// Determine the point where the aperture begins;
       n = ($abstime - tdelay + aperture) / period + 0.5;
       tstart = n*period + tdelay - aperture;
       @(timer(tstart));

// Determine the time where the aperture ends;
       n = ($abstime - tdelay) / period + 0.0;
       tstop = n*period + tdelay;
       @(timer(tstop));

// Implement switch with effective series resistence of 1 Ohm
       if (($abstime > tstop - aperture) && ($abstime <= tstop))
           I(hold) <+ V(hold) - V(Pin, Nin);
       else
           I(hold) <+ 1.0e-12 * V(hold);

// Implement capacitor with an effective capacitance of tc
       I(hold) <+ tc * ddt(V(hold));

// Buffer output
       V(Pout, Nout) <+ V(hold);

// Control time step tightly during aperture and loosely otherwise
       if (($abstime >= tstop - aperture) && ($abstime < tstop)) begin
           $bound_step(tc);
       end else begin
           $bound_step(period/5);
       end

   end
endmodule

Hi Andrew,

Thanks you so much for the help. You were correct - I was not editing the code using Cadence's default text editor (in my case "vi"). I prefer nedit and hence, once the "veriloga" basic text file was created by Cadence, I went ahead and closed the vi window and did all the editing (like cutting and pasting Ken's code) in nedit (opened through the Linux terminal).

As per your suggession I saved the code again by opening the veriloga code from within Cadence (in vi) and it compiled correctly and the simulation worked.

Do you know how I could change my default Cadence text editor to nedit (instead of vi)? This is not important, but could make my job easier.

Thanks again for all the help.
Sid