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problems with compiler directives (Read 4679 times)
Andrew Burton
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problems with compiler directives
Apr 13th, 2005, 6:54am
 
I am writing a testbench in VerilogAMS that needs to use the `ifdef compiler directive for each test. if a test is defined then I want to place in a netlisted module, this way I can controle its parameters without having to write the same source code again and again. However I can not do this inside an anaolg block. It works outside without a problem when the ifdef is defined. But when it is not defined the `else (as it is also outside the analog block), that says the test is not being run, will not compile and I get error messages.

Can anybody help with this problem?
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Andrew Beckett
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Re: problems with compiler directives
Reply #1 - Apr 13th, 2005, 12:19pm
 
Andrew,

Your description is not that clear. Please can you give an example (even if it is simplified), and also mention which tools you're using and the precise error message(s)?

Regards,

Andrew.
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Andrew Burton
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Re: problems with compiler directives
Reply #2 - Apr 14th, 2005, 1:04am
 
Hello Andrew,

Here is a simple example of the code that I am trying to execute:

`include "constants.vams"
`include "disciplines.vams"

//`define test1

module TEST (pin);
     electrical pin;

integer t1;
     
     
analog begin

`ifdef test1
     tim #(.th_start(1), .th_stop(4), .dir(1)) (*integer library_binding = "TESTBENCH";*) test1 (.tim(pin));
`else
     t1 = 1;
`endif



@(final_step) begin

      if (t1)begin
            $strobe("No EXECUTION OF test1");
      end
end

end      //end of analog process



endmodule


The code as it is above will compile and when simulated I get the correct message "No execution of test 1." However If I define test 1, the compilation fails. the error messages are:

Expecting a “=” or “<=” in an assignment (where the # is after tim)
Illegal expression in primary (after the first “.”)
Expecting a right parenthesis (after the first “,”)
Expecting a “;” (after the second “,”)
Illegal expression in primary (after the third “.”)
Expecting a “;” (after test1)
Illegal expression in primary (after the next “.”)
Statement not allowed inside analog block (at the final “;”)

With these messages I moved the `ifdef and the `else statements outside of the analog block. When defined this time, the test ran with success. However when undefined, the `else would not compile.

My compilation tool is : 05.10-s006  

I hope that my problem has been made a little clearer.

Thanking you,
Andrew
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Andrew Beckett
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Re: problems with compiler directives
Reply #3 - Apr 15th, 2005, 6:44am
 
The problem is nothing to do with the compiler directives. It's because you have an instance statement inside the analog block - structural things go outside the analog block. So if you removed all the 'ifdef stuff, but left the instance statement, you'd still have the problem.

Here's what I did instead:

Code:
`include "constants.vams"
`include "disciplines.vams"

`define test1

module TEST (pin);
 electrical pin;

integer t1;

`ifdef test1
 tim #(.th_start(1), .th_stop(4), .dir(1)) (*integer library_binding = "TESTBENC
H";*) test1 (.tim(pin));
`endif

analog begin

`ifndef test1
 t1 = 1;
`endif

 @(final_step) begin

  if (t1)begin
   $strobe("No EXECUTION OF test1");
  end
 end

end  //end of analog process

endmodule
 



Presumably the real code is a bit more complicated, since there's no analog behaviour here - but you hopefully get the point.

Regards,

Andrew.
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Andrew Burton
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Re: problems with compiler directives
Reply #4 - Apr 18th, 2005, 12:50am
 
Hello Andrew,

Thankyou for the solution, it worked perfectly. I have a few language reference manuals and I can not find the `ifndef compiler directive in any of them. You have helped me very much. And yes the sample code that I posted was just  one in which I used to reproduce the error.

Cheers,
Andrew
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Geoffrey_Coram
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Re: problems with compiler directives
Reply #5 - Jun 6th, 2005, 6:31am
 
`ifndef is not standard Verilog-AMS, though it's obvious what it should do, so I wouldn't be surprised to find it in commercial simulators.  For portability, you should use:

Code:
`ifdef test1
`else
t1 = 1;
`endif
 

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