HI teachers,

I am currently designing a high speed comparator based on Yin, Eynde and sansen's design (solid state journal). The comparator consists of differential input stage, d-flip flop stage and SR-latch output stage. Now I need to simulate for the comparator's offset voltage using HSpice. How do I go about doing this? what syntax do I need to use to perform the offset voltage simulation? Is there any good reference on this topic?

cheers

[quote author=shariman  link=1115860584/0#0 date=1115860580]
How do I go about doing this?
[/quote]

Insert a DC-source on one of the input pins and perform a DC-sweep, say +/- 20mV and inspect the output waveform.

If you have access to the bulk pin of the input transistor, you can change the VT by inserting a DC-source between ground and bulk of one of the input transistors and perform another DC-sweep.

You can also use monte-carlo simulation if your transistor models support statistical variations of parameters.

Many features are depending on what simulator you use. Maybe it would be possible to say more if you tell which simulator you use.

Glad to see you here ! Ya wei !  :D
[quote author=ywguo  link=1115860584/0#1 date=1116219697]Hi, Shariman,

Basically I think the offset voltage simulation is based on your estimation of the mismatch of the relative transistors. Ideally it is of zero offset voltage for a differential comparator. The SPICE model doesn't contain the transitor mismatch parameters. So you can't simulate the offset voltage unless you modify some parameters or modify the dimensions of the relative transistors. Of course a wrong estimation of the mismatch will result in a wrong offset voltage.  :)

Best regards,
Yawei [/quote]