hi all:
Pardon my ignorance. I have a question about CDR, please give me some advice.
I have designed a 2.5G CDR with half rate PD. I follow the Razavi paper,
A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector, May 2001.

This CDR contains linear half rate PD, interpolation type ring VCO, charge pump and loop filter. I use the same architecture in the paper. All circuits simulate by Hspice.
I think that each block works well(maybe not).

However, when I connect each block together, the retiming data lose some bits. It will random lose a bit within random period.
In order to solve the question, first I get rid of the charge pump and loop filter. I directly input the correct VCO tuning voltage to make VCO oscillate at 1.25G. But the result is still incorrect. Then I replace the VCO to the ideal source(1.25G square wave) and I found that the retiming data is correct.

According to the situation, could I consider the VCO as a problem?
I think that the VCO may have bad phase noise. (I don't have software to do the simulation. or maybe it can be simulate at Hspice) Is that correct? or it results from other factors.

The VCO is a five stage interpolation ring oscillator.

In order to reduce the jitter, I try to make the waveform of VCO to be symmetric; therefore, I add the buffer amplifier(cherry hooper amplifier) in each stage.

Could someone give me some suggestion to solve this problem?
Thank you in advance.

yli

Yli,

I don't think phase noise is the problem in your simulations. When you run transient simulation, there is no phase noise present. For phase noise to be considered by the simulator, you need to run a noise simulation (check your simulator manual).

You mention it works with an ideal clock source. This can be related to the low output impedance of the source compared to your VCO. It can also be related to the phase, which is certainly different than the one of your VCO with a constant input voltage. Remember, frequency lock is not sufficient to guarantee low BER. Instead of putting an ideal clock source into your schematic, you should try with an ideal VCO (macromodel). On the other hand, check if your PD input capacitance is not loading the VCO too heavily? Check the amplitude of your VCO signal at the PD input once the loop is closed.

BTW, typical values for BER are in the order of 1e-12, not 1e-6.

Good luck

Paul