Ericjohnson,

The earliest paper presented the 1.5bit/stage algorithm (RSD) is by B. Ginetti, P. Jespers, "A 1.5 Ms/s 8-bit Pipelined RSD A/D Converter," in European Solid-State Circuits Conference Digest of Technical Papers, pp. 137-140, Sep. 1990. But I havn't that paper since only ESSCIRC papers after 1996 are availabe on its website. But I have another paper by G. Ginetti, et al., A CMOS 13-b cyclic RSD A/D converter, JSSC, July, 1992. I hope it will be helpful for you.

Best regards,
Yawei

Eric

you can also try to find Jesper's book. I find it well written, but sometimes too concise on the details:
http://www.oup.co.uk/isbn/0-19-856446-5

Anyway this scheme has been used by many people, so you should be able to find many papers on it. It seems to me it's just about addition of output codes, but make sure to use the right format and offset. There's also the following Maxim appnote:
http://maximic.com/appnotes.cfm/appnote_number/1023
although, I dislike some statements like "The implication is that none of the flash ADCs in Figure 1 has to be as accurate as the entire ADC." This may be true for the gain error, but the non-linearity of any stage directly affects the overall non-linearity directly. So be careful...

Paul

Ericjohnson,

You are right.

Yawei