Hi!

I am new to this forum. My question is, does anyone have an idea of a good test-bench for simulating the Common-Source Amplifier? I mean, how to bias the active transistor(dc voltage at the gate) such that the output is maintained at a particular value, for instance (vdd+vss)/2. The biasing scheme need not be practical. Its just for the sake of tesing the circuit.

At present I am using a VCVS (high gain)to read the output voltage and am using a large capacitor connecting the output of the VCVS to gnd (to bypass the AC signal to gnd) and using a large inductor in series to the output, to further block the AC. This filtered output is connected to the gate of the NMOS (active transistor), I have tried 2 options:

1) use a large coupling capacitor, connect the output of the VCVS to the gate directly, and the input AC signal is fed through the coupling capacitor

2) I insert another VCVS in series to the input AC source. This VCVS (VCVS2) is controlled by the output of the first VCVS.

The VCVS1 actually compares the output of the CS to (vdd+vss)/2 and has a very high gain. Thus a feedback loop is formed which should force the output DC level to be (vdd+vss)/2. However, I have some problems with this. Sometimes its giving me carzy results. Any suggestions?

Or does somebody have a better idea?

regards,

Taj