jbdavid
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VSDE/VCME are certainly CAPABLE of doing the characterization.. but few people pushed it far enough to get all the Common (say Artisan) standard cells supported, so you'ld probably have to setup additional characterizations to completely cover your libarary..
I think there are other solutions that (voltagestorm?) that you could use right out of the box for DIGITAL STANDARD CELL characterization (not something I've every actually had to do).
Its POWER comes to play if you have any ANALOG blocks in your library that you need characterized ANALOG behavioral models.. Where the CURRENT methodology doesn't support fixed models with parameters obtained from a lib/tlf file (someone thought it wouldn't be useful in an analog flow!) you can create a verilog-A model from a template with default parameters obtained from the simulation results. One other draw back is that it only support Verilog or Verilog-A models.. There is no support for characterized Verilog-AMS models..
It was a good start but I'd say its relatively unfinished for what I need.. Jonathan
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