James
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snowfiled
Posts: 32
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Andrew,
you are right, I broke the loop and simulate the VCO control voltage vs. output frequency. It's consistent with the close loop result.
Sheldon,
I watch the control voltage to tell if the PLL is locked. After the control voltage is flat, I think it's locked. But even the Vcontrol is flat, when I zoom in it to watch closely, there is small ripple, around 1.5mV.
I am also curious about how to simulate the loop gain of the whole PLL, the capture rang and the lock range. I read the cdsdoc about the pllLib in Cadence, but have no idea how to apply it to my PLL. Is there any way I can get these information by simulating on transistor level?
For loop gain, I get it by using a software of "PLL Design Assistant" written by a professor in MIT. I found my loop gain is 1.128e13. In the software simulation, it indicates increasing divider ratio will decrease the loop gain. I will simulate it in the transistor level.
But I found an interesting fact. When I only simulate the PFD+CP+loop filter, if I add two identical pulse source in the inputs of PFD, in theory, the output of Charege Pump should be constant, thant means whent the control voltage should be constant after the inputs of PFD are identical. But the simulation shows the CP output go up. That means even the reference clock and the output clock are exactly same, the control voltage of VCO cannot be constant. I think this fact can explain why the PLL need a phase error to keep the Vcontrol be constant. If I change the ratios of the pmos and nmos switches in CP, the CP output can go down or still go up but by a different slope. If I change the current sink in CP, I also can watch the same effect on CP output. I cannot understand this result.I am confused.
Best
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