How do I make a current sense in Verilog-A?

Eugene -
I think the recommended way to sense a port (terminal) current is with

LHS = ... I(<in>) ... ;


-Geoffrey

Thanks for your reply.

Yes, I want to sense a port current and I've noticed that I(in) short circuits in to ground.

However, I've tried your advice, but it didn't work. I get the following error messages:

In file src/switch_sense.vla line     52:
        LHS sense=I(p);
            ^
[Failure] Syntax error : received IDENTIFIER
         while expecting '('
                      or '[' or '='

and

In file src/switch_sense.vla line     52:
        LHS=I(p);
        ^
[Error] Symbol LHS has not been defined
Error: (valog) Compilation: Analysis failed.

Eugene - Yes, that is special syntax only for ports (aka terminals).

One typical use of a current sensor is a controlled source:

Code:

module ccvs(in, out);
  inout in, out;
  electrical in, out;
  parameter real gain = 1;

  analog begin
    V(out) <+ gain * I(in); // shorts "in" to ground
  end
endmodule 

As noted before, this shorts "in" to ground, and then measures the current flowing through this shorted branch to generate the output voltage.

One might use the I(<port>) syntax in a more complicated module
Code:

module bjt(c,b,e);
  inout c,b,e;
  electrical c,b,e;

  real ic, ib, ie;

  analog begin
    // put BJT equations here

    ic = I(<c>);
    ib = I(<b>);
    ie = I(<e>);

    $strobe("Terminal currents: i(c)=", ic, " i(b)=", ib, " i(e)=", ie);
  end
endmodule