I have already asked this question in the thread about the noise in PFD/CP but, as there were no responses, I dare to ask it again here  :)

I have extracted the output noise of PLL blocks using PNoise analyses as described in Ken's paper and built a linear phase-domain PLL model. The simulated results are pretty close to the measurements from the chip and the phase-domain model shows that the low-offset in-band phase noise of PLL is donimated by PFD/CP block.

The CP is a simple single-ended charge pump with switch in source. I looked at the PFD/CP output noise contributors and the major noise was due to flicker noise of NMOS cascode bias transistors in CP which is logical. But after I increased the length of the bias transistors, the next major noise contibutors were transistors in the inverters which serve as buffers for the UP & DOWN signal between PFD and CP. The buffer is a chain of 2 inverters, so Cadence shows that noise comes from the NMOS in the second inverter. If I further on increase both W&L in the second inverter, then the major noise contributors are transistors in the 1st inverter.

What can be an explanation for that? Does it mean that, according to simulation, the main output noise is at the moment of switching UP & DOWN signals (when these signals are near inverters tresholds)? Is such noise model of PFD/CP in PLL realistic?  ???

A few words about simulation setup: The delay between Fv & Fr is zero (I want to get the noise at the lock state). The PFD clock freq is 600 kHz, in PSS number of output harmonics is 30, in PNoise maxsideband=30, I am looking at noise at 1-10kHz.