Hello All,
            I am looking for good reference to design 10-bit 1Msamples/sec, 2-stage recirculating pipelined ADC. i have single-ended input. I will be very glad if you can help me with this.

Thanks,
RK

Hello Yawei,
                 Thanks for the quick response.
I am talking cyclic ADC.

I have gone through that paper you have referred.

   I forgot to write one more specification of the ADC earlier, the input swing of the ADC is 0 to 3V and my VDD = 3.3V and VSS=0V.  So ADC's input stage needs to scale(1/2) the inputs in order for the ota in the MDAC/Sample and Hold to operate.

  I want to confirm another point with you, if I have single-ended analog input and I use differential MDAC structures having other input at common-mode.  Will I still be having the advantage of offset cancellation because of the differential structure? or do I need to convert my single-ended input into differential initially to have that advantage.

Your comments will be very valuable to me.

Thanks,
RK