Hi,

I am designing an R-ladder DAC, and would like to get some feedback about the best way to minimize the INL. Because it is a series connection of resistors from
end to end, I see no solution for reducing the effect of linear gradients etc.

Does anyone have any suggestions on how to design or lay it out for good linearity?

Thanks
Vivek

Vivek, there's a useful book "Analogue-Digital ASICs" Ed R S Soin et al, published by Peregrinus (UK) 1991 ISBN 0 86341 259 9
This has a chapter on layout (chapter name is "Practical aspects of mixed analogue-digital design"). This discusses process variations, noise etc.

I've used the recommendations for many years with success, particularly for common centroid schemes, MOS switches and switched capacitors.

It has a really good example of DAC resistor ladder layout.
If you'd like a pdf just send me a message.

- Rob