As far as I know, there is no automatic generation of behavioral model for the components.

Since you want fast simulation of the whole PLL, I wonder whether you have tried fast-Spice tools such as Hsim or Ultrasim.

Baolin

Greetings,

To answer the questions yet another way:

1) see Andrew's append

2) There are commercial products that do generate
    Verilog-A models from circuit schematics. However
    if you want to simulate a PLL then this approach is
    probably not required.

3) ModelWriter is a tool that makes it easy to modify
   the models without having to write VerilogA code.
   However, there are only limited number of templates
   in the libraries provided and only Verilog-A are
   supported.

BTW,   DCM, Design Characterization Module, was the
Antrim name for the product. The new name is VCME,
Virtuoso Characterization and Modeling Environment.

If you are really only interested in PLL simulation then
you should not have too many issues. The models in the
Designer's Guide Analysis section are written in Verilog-A
and work well in Spectre. Also Cadence provides several
behavioral modeling libraries. Please look at the examples
in bmslib since they include both Verilog-A and Verilog-AMS
examples.

In reality, if you use AMSD then you will only need two
models, a charge pump and a VCO. The VCO has been
covered in another thread in detail and you can re-use
Ken's charge pump. The logic can alll be done very
effectively using gate level/structural Verilog-D. There is
one cavaet, remember that the PFD is a mixed-signal
circuit and you must include the delays for all the gates.

Finally, just wanted to go back to the point about
generating behavioral models from schematics. That
technology is progressing, however, in many cases you
do not need it. What you are interested in the behavior
of the overall system and to understand that you do not
need the generate models that exactly replicate the
architecture of a particular circuit. For example, when
simulating with an op-amp, you want to model open-loop
gain, bandwidth, slew rate, ... The fact that the op-amp
is a folded cascode or a telescoping is not interesting as
long as you model the relevant behavior. (In the
aftermentioned case, input common level and output
swing need to be modeled).  So unlike most IP, behavioral
models are almost 100% re-usable.

The other issue is that fitting behavioral models can
be as hard as writing behavioral models.This is where
VCME really helps. It includes both behavioral model
templates and the testbenches required to characterize
the blocks.

                                                       Best Regards,

                                                          Sheldon

Hi, Guys,

From technology point of view, real automatic generation of nonlinear model for schematic seems very hard. The black-box approaches I know such as neural netowrk, Voltera series, and nonlinear model order reduction are not that mature in my opinion. Anyone knows what method the Antrim tool uses? Antrim promised a lot of great things including analog synthesis, which didn't turn out that well

If it is not really "automatic", then it is probably easier.

Thanks,

Baolin

Thank you all for your quick and analytical answers.

Something final. I have found some very usefull veriloga models. How can i get a symbol from a veriloga model (In spectre RF), in order to import it in my schematic?

Thanks

Since Sheldon (art?) didn't answer this, I will..

[quote author=byang  link=1127746857/0#5 date=1127859641]Hi, Guys,

From technology point of view, real automatic generation of nonlinear model for schematic seems very hard. The black-box approaches I know such as neural netowrk, Voltera series, and nonlinear model order reduction are not that mature in my opinion. Anyone knows what method the Antrim tool uses? Antrim promised a lot of great things including analog synthesis, which didn't turn out that well

If it is not really "automatic", then it is probably easier.

Thanks,

Baolin [/quote]
It is Automatic, but it's not "Black Box" .. it is actually template driven.. you select the circuit and the template that best matches your circuit.. (chargePump, VCO ,And gate etc) then you match the actual pin names to the pin functions in the model and define the simulation conditions (sources, supplies and loads) and now the problem is sufficiently constrained (if the template has been developed.. and if that template fits what you really need. )
this is something I plan to use to keep internal IP up to date and validated..
Jbdavid