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How to speed-up the simulation of PLL (Read 614 times)
chip
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How to speed-up the simulation of PLL
Oct 10th, 2005, 2:01am
 
It's lock time is about 100us
I use nanosim to simulate it,and i set up properly for the trade-pff between accuracy and speed - i think so:)
but the simulation is too slow,as pre-layout simulation,it takes 4 days to finish the simulation about 100us
Can someone guys share some experiences about speed-up the simulation of PLL?

thanks
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byang
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Re: How to speed-up the simulation of PLL
Reply #1 - Oct 10th, 2005, 8:51am
 
Chip,

How big is the PLL? How much is the number of device elements? How fast/slow is Spice?

If you put more analog subcircuits into one partition, that might help.

Baolin
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