danmc
Community Member
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Posts: 35
Boston
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I'm trying to simulate a frequency divider (built with static CMOS logic) using PSS.
If I run a transient sim, everything looks good. All the waveforms are what they should be. When I run PSS however, I'm unable to get it to converge. I selected my clock source as the Fundamental Tone and set it as a Large signal. For the beat frequency I picked the divider output frequency (1/24th of the clock source). For tstab, I picked a time which is long enough for the divider to fully go through a couple of output cycles so I've hopefully flushed out any wierd initial states.
In all 20 pss iterations, I see the same large value for the convergence norm: Conv norm = 72e+03
Also, once I get past this problem I'll want to look at the noise at the output rising edges. Is there a way to automate the selection of the time for the timedomain noise? It would see like if I could figure out how to make a spectreRF compatible S-R flip-flop, it would be simpler to set the (noiseless) flip-flop with the divider output and reset it with something derived from my clock source. Then I wouldn't need the timedomain option but could go from the phase noise output directly. Comments on this?
Thanks -Dan
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