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RobertZ Community Member Offline the art of analog Posts: 55 San Diego, CA	how to pass a string in Verilog-A Nov 01^st, 2005, 10:56am Hi, all, I want to pass a string as a parameter, but don't know how to define and use string in verilog a (not verilog ams). I tried like this: parameter string string_name = "abc" but there is a syntax error, which complains "string" Thanks a lot, -driveforce
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RobertZ

Community Member

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the art of analog

Posts: 55
San Diego, CA

Re: how to pass a string in Verilog-A
Reply #1 - Nov 1^st, 2005, 12:27pm

I found one article inside this forum, which is quoted here.
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
Verilog-AMS LRM 2.2 adds support for string parameters, which must be declared as such:
parameter string outfile = "foo.dat";

Alas, Accellera has not yet voted on these extensions, so vendors have not implemented them.

The current support for "strings" in Verilog-AMS is the variable type "reg" (see section 2.6 of the current LRM); also, there is a format specifier "%m" that is supposed to return the hierarchical name of the instance. There's an off chance that you can use these, eg,
reg [8*40:1] outfile;
integer fh;
outfile = "%m";
fh = $fopen(outfile);
or
fh = $fopen("%m");
though I somewhat doubt this will work (%m probably only works in $strobe).

You might be able to do something like
parameter integer blocknum=0;
integer fh;
reg [8*40:1] outfile;
outfile = "output_";
outfile[8] = blocknum+48; // 48==ascii offset of "0"
fh = $fopen(outfile);

-Geoffrey

<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

But it didn't work in my simulator.
after I use keyword "reg", an error notice appeared:
Warning from spectre during SpectreHDL compile.
"/projects/driveforce/lib/private/mylib/temp/veriloga/veriloga.va",
line 10: Warning: `reg' is a future reserved keyword, parsing as
identifier.Error found by spectre during SpectreHDL compile.
"/projects/driveforce/lib/private/mylib/temp/veriloga/veriloga.va",
line 10: "reg [8*30:1] File_name;<<--? "
"/projects/driveforce/lib/private/mylib/temp/veriloga/veriloga.va",
line 10: Error: syntax error

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Thanks,
Robert

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Jess Chen Community Fellow Offline Posts: 380 California Bay Area	Re: how to pass a string in Verilog-A Reply #2 - Nov 1^st, 2005, 1:15pm To my knowledge, you cannot pass a string as a parameter into a VerilogA module, at least not in Cadence's VerilogA. Although such a capability would be really, REALLY, useful, especially now that we have table models available.
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RobertZ Community Member Offline the art of analog Posts: 55 San Diego, CA	Re: how to pass a string in Verilog-A Reply #3 - Nov 1^st, 2005, 3:34pm Hi, Jess, Thanks for your reply. I made it work by Spectre HDL. -driveforce btw, I noticed you wrote lots of verilog-a example in cadence.
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Jess Chen Community Fellow Offline Posts: 380 California Bay Area	Re: how to pass a string in Verilog-A Reply #4 - Nov 1^st, 2005, 4:24pm I worked at Cadence from 1995 to 2000. While I was there I worked on the rfLib, pllLib, j/k models, and some of the AWB library. I wrote the J-model in rfLib using SpectreHDL for exactly the reason you found.
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Andrew Beckett

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Life, don't talk to
me about Life...

Posts: 1742
Bracknell, UK

Re: how to pass a string in Verilog-A
Reply #5 - Nov 1^st, 2005, 9:55pm

Jess,

Actually this can now be done with Verilog-A. I used:

Code:

parameter filename = "test.out";

within the code I then did:

Code:

$display("%s\n",filename);

and I can quite happily pass filename="something" on the instance line in the spectre netlist.

This certainly works in MMSIM60 (not tested it in earlier versions). In MMSIM60 USR2, there is going to be support for following the 2.2 LRM way of doing:

Code:

parameter string filename = "test.out";

Regards,

Andrew.

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RobertZ

Community Member

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the art of analog

Posts: 55
San Diego, CA

Re: how to pass a string in Verilog-A
Reply #6 - Nov 2^nd, 2005, 2:24am

Hi, Andrew,

yes, I tried what you said, file names can be passed.

but I have another problem.
I tried to instance a pwlf voltage source in verilog-A, as following:
vsource #(.type("pwl"), .file("data.txt"), .delay(delay_time), .offset(dc_offset)) v1(plus, minus);

an error said "delay" is an reserved name for simulator library function.

by the way, where should I instance vsource?

Thanks
-driveforce

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Thanks,
Robert

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Jess Chen Community Fellow Offline Posts: 380 California Bay Area	Re: how to pass a string in Verilog-A Reply #7 - Nov 2^nd, 2005, 11:26am Thanks for the tip Andrew! -Jess
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Andrew Beckett Senior Fellow Offline Life, don't talk to me about Life... Posts: 1742 Bracknell, UK	Re: how to pass a string in Verilog-A Reply #8 - Nov 4^th, 2005, 4:55am Driveforce, I answered your delay question in the other thread where you posted this - http://www.designers-guide.org/Forum/?board=verilogams;action=display;num=113106... Andrew.
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