Hi friends,
I have a symmetric load differential VCO.How do I take care of the output load considerations in my design? Or how do i design my VCO with fanout considerations.

Thanks in advance.

Thanks,
But what I meant to say that, if I use this VCO in a PLL circuit, which in turn is acting as a clock.Then there has to be certain consideration for the load which the PLL has to drive.This is like fanout consideration in the digital design side.Since it will be the VCO which has to drive the load so how do I design a VCO taking this fanout or load consideration.

Well normally u have a buffer in between so you can design them sort of independently.

can ushare the buffer design?? i designed my VCO keeping 1pF at the load but if i increase load capacitance,the oscilation frequency increases.Please let me know the buffer design