vijay
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Thanks, But what I meant to say that, if I use this VCO in a PLL circuit, which in turn is acting as a clock.Then there has to be certain consideration for the load which the PLL has to drive.This is like fanout consideration in the digital design side.Since it will be the VCO which has to drive the load so how do I design a VCO taking this fanout or load consideration.
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