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Sherki

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understanding this schematic
Nov 18^th, 2005, 11:02am

Hi,

here is the schematic of current comparator : if Iin is bigger than a threshold current (set thanks to Ibias and the 2 resistors) the output, Sou is low...
Note: W(P2) = 5 W(P3)
W(N1) = 5 W(N2)

But could somebody explain to me how it works in details? I mean how the voltages change and influence the currents in the mirrors? THANKS A LOT

Sherki

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huber

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GO BEARS!

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Los Angeles

Re: understanding this schematic
Reply #1 - Nov 18^th, 2005, 3:02pm

P1, P2, N1, and the left resistor set up a bias voltage at the gate of N2. The core of the comparator is the common gate amp formed by P3, N2, and the right resistor. P4/N3 is just a common source amp that serves to provide more gain. If Rright = 5*Rleft, then the bias/common gate circuits are balanced and the circuit will compare Iin to 0. If Rright is smaller than 5*Rleft, then Iin will be compared to a positive current. If Rright is larger than 5*Rleft, then Iin will be comared to a negative current.

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ipierre New Member Offline Posts: 3 South Korea	Re: understanding this schematic Reply #2 - Dec 5^th, 2005, 10:25pm Given 5*Rleft=Rright, If Iin is postive(or negative) current source, The source of N2 will be up(or down). then The drain of N2 is up(or down) in saturation. In results, the output sou is down(or up). Best regards. iPierre (Novice)
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aamar

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Germany

Re: understanding this schematic
Reply #3 - Dec 6^th, 2005, 1:44am

If you want to look for it as a group of current mirrors, then your circuit includes two current mirrors. The first is P1/P2 and the second is N1/N2.
From the first mirror Ibias will flow also in P2/N1 in steady state, biasing the source of N1 to Ibias*Rleft. Rleft is used to stabilize the operating
point, by its negative Feedback effect on N1, because when current increases in P2/N1 for any reason, the drop on Rleft will increase the source node voltage of N1 high (above the steady state value), reducing the Gate-Source voltage of N2, which will reduce the current back to the steady state value (biasing circuit).
The second current mirror between N1/N2 will bias the P3/N2 with the same current Ibias, which will adjust the source of the N2 to Ibias*Rright, the same like we mentioned before the Rright will have a negative Feedback
effect on the source follower N2, but this time the current change will be intentionally using the Iin, in the way that when it is high enough above a certain threshold current it will raise the source node voltage of N2 to
a level which can turn N2 off (given that the gate voltage of N2 is constant, from the bias circuit), then when it is turned off the output of P3/N2 will be VDD, which will be further amplified by the output stage (P4/N3) (driving
the N3 strongly ON) so the Sou will be low (conclusion: Iin is High, Sou is low) and you can conclude the second case when Iin is negative.
I wish my discussion was clear.

Best regards

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jerome Kirscher Guest	Re: understanding this schematic Reply #4 - Dec 19^th, 2005, 6:28am Thank u all for your explanations One more question: How can I set the threshold on the Iin current to 600�A, given that the currents flowing through : P1 = 10�A, through P2 = 50�A, through P3 = 10�A and through P4 = 10�A Again thanks for helping me! J�r�me
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Sherki New Member Offline Posts: 2	Re: understanding this schematic Reply #5 - Dec 19^th, 2005, 6:35am I was not logged in when I posted my new question, so now you are all knowing my name ! j�r�me, alias Sherki
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baohulu

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china

Re: understanding this schematic
Reply #6 - Jan 16^th, 2006, 9:22pm

i think the key to set the threthold is that the voltage of the two resister is the same,so

I2*Rleft=(I3+Ith)*Rright where I2,I3 is the drain current of P2 and P3 respectively

in your question, I2=50ua, I3=10ua, Ith=600ua, so Rleft/Rright=61/5

but I have a question about the demand, in cmos process, the resister value is rough, so does the control
by the resister is accurate?

jerome Kirscher wrote on Dec 19^th, 2005, 6:28am:

Thank u all for your explanations

One more question:
How can I set the threshold on the Iin current to 600�A, given that the currents flowing through : P1 = 10�A, through P2 = 50�A, through P3 = 10�A and through P4 = 10�A

Again thanks for helping me!
J�r�me

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ywguo Community Fellow Offline Posts: 943 Shanghai, PRC	Re: understanding this schematic Reply #7 - Jan 18^th, 2006, 9:39pm Hello, Jerome and Baohulu, The point is that keep relative accuracy of those two resistors in this circuit. So don't worry about the absolute value. Best regards, Yawei
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