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chase.ng

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Phase lock loop frequency divider
Nov 21^st, 2005, 10:30pm

Hi all, need some help over here regarding PLL frequency synthesizer.

I am familiar with PLL that provide clock signals to the core of a digital IC. The VCO output is a square wave and the divider and hence the PFD can be easily implemented using CMOS logic.

However, I am kinda confused when I looked at the PLL for frequency synthesis in radio communication where the VCO actually output sine wave.

My question is if the VCO output is sine wave, how to divide the frequency of the output? Are we still using digital divider in this case? If the sine wave is to be converted to squarewave before feeding into a digital divider, isn't it going to impact the phase noise performance of the PLL?

Thank you in advance.

Chase

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Chase

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sheldon Community Fellow Offline Posts: 751	Re: Phase lock loop frequency divider Reply #1 - Nov 23^rd, 2005, 6:08am Chase, What if you used an ECL[or Source Coupled Logic] based divider? Using SCL logic would relax the requirements on signal levels and reduce the noise of the divider. Best Regards, Sheldon
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chase.ng Community Member Offline Posts: 77 penang/malaysia	Re: Phase lock loop frequency divider Reply #2 - Nov 23^rd, 2005, 7:22pm Hi Sheldon, Thanks for the advice. So what you mean is that the divider will still be digital in nature? And we just feed the analog sine wave to the divider and get the lower frequency digital square wave at the output? Thanks and Regards, Chase
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sheldon

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Re: Phase lock loop frequency divider
Reply #3 - Nov 25^th, 2005, 3:24am

Chase,

Yes a ECL[SCL] gate does not require very high drive
levels to switch completely. You could also put a pre-amp
in front of the divider stage, e.g., two diff amps, to square
the sine wave up before division.

You could also break the divider into two stages a high
speed pre-scaler with a fixed divide ratio and a
programmable divider. Then you might be able to make
the prescaler out of high speed logic and divide down to
a low enough frequency to use regular CMOS logic for the
programmable counter.

However, you will need to verify that what ever approach
you select is appropriate for your design.

Best Regards,

Sheldon

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chase.ng Community Member Offline Posts: 77 penang/malaysia	Re: Phase lock loop frequency divider Reply #4 - Nov 27^th, 2005, 8:56pm Hi Sheldon, thanks a lot...
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Juan F. Ex Member	Re: Phase lock loop frequency divider Reply #5 - Dec 9^th, 2005, 8:40am Hello, There is a good discution over the kind of logic that should be used for FS in the thesis by Hamid R. Rategh at standford university titled "Low Power Cmos Frequency Divition and synthesis at Multi-Ghz Frequencies". There are also some tips to designs low power SCL dividers. Bye
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henry98

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Re: Phase lock loop frequency divider
Reply #6 - Mar 11^th, 2006, 12:30am

Sheldon,
I have also met the same problem. When you added the two differential preamplifiers between the VCO and the divider, these two differential preamplifiers may not be switched fully by the VCO output voltage. Especially f or the first one.

For example if the VCO output voltage is between 1.8 to 2.5v; We can use the first Pre_amplifer to increase the output swing, if amplifying 2 times, then we can got the output swing: (2.5-1.8)*2=1.4v. But this first stage pre_amplifier maybe not fully swithched by the VCO output voltage(1.8 to 2.5v), so after first amplified, the votage maybe in the range 0.9 to 2.3v. And it can't reached to vdd=2.5v. That means the first pre_amplifier can't be fully switched by the VCO output swing.

IF such things happened, Could these pre_amplifiers still be thought as work very well?

Thanks

Henry

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ywguo Community Fellow Offline Posts: 943 Shanghai, PRC	Re: Phase lock loop frequency divider Reply #7 - Mar 11^th, 2006, 12:50am Hello, Henry, Don't worry if the amplified signal is toggle from 0.9 to 2.3 or 0.9 to VDD. It is good enough only if the amplified signal can drive the load. It depends on the input high voltage of the successive gates. Best regards, Yawei
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henry98 New Member Offline Posts: 4	Re: Phase lock loop frequency divider Reply #8 - Mar 20^th, 2006, 10:26pm Hi.Yawei, I can't understand very well what's your meaning in the last sentence: It depends on the input high voltage of the successive gates. Can you explain it more details? Thank you very much Henry
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