Hi,

I am facing a little problem in designing an input matching network for a 2.4G LNA. The problem is I am working in 65nm process and my bias current is limited to .75mA. So my cgs is very small, abt 50fF. Hence I have tried doing an inductive degeneration Ls to give gmLs/ Cgs = 50 ohms...however to tune out the large imaginary part, I need a very large inductor at gate...abt 50n..and that has a very poor Q of abt 2...So I fail to match.
I have tried another alternative, to put a parallel cap across Cgs to increase its value to arnd 300fF..that way I get matching, but because by adding extra cap, I am reducing fT, I am hurting my gain a lot and so its not that good.
If someone cud suggest a better/new way of dealing with thid, it will be very helpful.
Thanks and Regards,
Joy