I would realise a polarisation stage in veriloga language.
I need to instantiate 80 similar polarisations stages (PolaStage<79:0>).
Each stage has the same input current (in) but not the same output voltage (out<79:0>).
So if I have a current source of 80µA, each stage see only 1µA.

To simplify my problem, I wrote :

>
> branch (in,gnd) toto
>
> analog begin
>     outval = K * I(toto);
>     V(out) <+ outval;
> end




the parser didn't see error but when I start spectre, I have a fatal error  >:( :

The following branches form a loop of rigid branches (shorts) when added to the circuit :
PolaStage_0:in_flow (from in to 0)
PolaStage_1:in_flow (from in to 0)
PolaStage_2:in_flow (from in to 0)
PolaStage_3:in_flow (from in to 0)
....

Is it really impossible to write a veriloga close to the schematic in this case ??
Thanks for your help

Ben

I'd lean towards using a bus in the module

module polar(in, out);
inout in;
inout out[79:0];
electrical in;
electrical out[79:0];
parameter real K = 1;
real ibr;
genvar idx;

analog begin
 ibr = I(in,gnd);
 for (idx=0; idx<80; idx = idx + 1) begin
  V(out[idx]) <+ K * ibr;
 end
end
endmodule

If your gain K differs, then you'd need
 parameter real K[79:0] = { };
and you'd need to put 80 values in the braces {}.

I'm still unsure whether the input current is supposed to be split among all 80 stages, or whether each one is supposed to depend on the full value (which is what my suggestion does).

I mention this for later readers of the forum, as you've solved your problem.