Hi, Sid,

I think the jitter in the input signal affects the testing because that jitter deteriorates the SNR of the input signal. However, the SNR of the input signal affects the testing directly. So just find the SFDR, SNR and THD parameters in the manual of your signal generator.

To test such a high resolution ADC it is a good idea to filter the input signal if you have not good enough signal generator.

Look into this problem from another perspective, the clock source and input signal are locked to the same reference timing clock. So we assume the clock source is phase locked to an sine wave w/o jitter (the input signal). So we only need know the jitter of the clock source.


Best regards,
Yawei