Hi,

maybe this topic is a bit too trivial for some of you, nevertheless...

Let's assume I want to model (Verilog-AMS, so no SPICE macro-modeling) a CMOS OTA with the dominant pole at its output (e.g. symmetrical CMOS OTA).

In most code snippets I have seen, most people tend to put a Laplace transfer function inside the OTA model and include the output impedance using a real parameter, finally using a statement as this:

I(outp,vss) <+ V(outp,vss)/rout


My question is as follows: if the capacitive load (SPICE primitive) of the AMS-model of the OTA  changes, will the output pole of the overall model change?

Or: thus the real parameter 'rout' interact with a SPICE primitive to form a pole 1/(2*pi*rout*C), which can, e.g. be seen in an AC analysis?

Kind Regards

Peter