Hello people,

I need some help. I am modelling an oscillator using verilog AMS.
The model comprises three blocks - mixer, amplifier and phase-shifter.
These modules are written at the behavioral level and instantiated in
the oscillator module.
An oscillator has feedback in it.
When I give a sine wave input to the model, it should be amplified and
then part of the output is fed back to the input using a mixer. So the
output is expected to be an increasing sine wave , growing in amplitude
in each cycle.
On the contrary the output is observed to be a constant amplitude
sinewave over all cycles.

Is it possible that all blocks try to compute their outputs at the same
time?
In such a scenario, the feedback system cannot function correctly.

Please help me debug this issue.
The code and testbench are as shown below

CODE

// Middle level high level oscillator model without any Noise //

`include "disciplines.vams"
`include "constants.vams"
`timescale 1ps / 1ps

module oscillator(out,in);
output out;
voltage out;
input in;
voltage in;
voltage vx,vref;
parameter real amplifier_gain = 15 from (-inf : inf);
parameter real test_frequency = 100k from (0 : inf);
mixer m1 (vref,in,vx);
amplifier #(.gain(amplifier_gain)) a1 (out,vref);
phase_shift #(.freq(test_frequency) , .gain1(amplifier_gain)) ps (vx,
out);
endmodule

module amplifier(out,in);
input in;
output out;
voltage in, out;
parameter real gain = 15 from (-inf : inf);
analog begin
   V(out) <+ (gain * V(in));
    end
endmodule

module phase_shift(out,in);
input in;
output out;
voltage in, out;
parameter real freq = 10k from (0 : inf);
parameter real resonant_freq = 60M;
parameter real beta = 0.1; //beta is a function of the circuit
components of the module and also the resonant frequency.
parameter real toff = 1.6n ;
parameter real damp = 10M;
parameter real gain1 = -6 from (-inf : inf);
parameter real sampler = 1/resonant_freq;
real flag,flag1;
real phase = `M_PI;
analog begin
@(initial_step) begin
flag1 = 0;
     end
flag1 = 1;
@(timer(toff,sampler)) begin
flag = V(in);
$display("%g",flag);
                   end

V(out) <+  flag1*beta*V(in);

      end
endmodule

module mixer(out,in1,in2);
input in1,in2;
output out;
voltage in1,in2,out;
real trial1,trial2, trial3;
analog begin

        V(out) <+ (V(in1)+ V(in2));
end
endmodule



TESTBENCH

`include "constants.vams"
`include "disciplines.vams"
`timescale 10ps / 1ps
module mid_wo_noise();
wire out;
voltage in;
electrical gnd;
ground gnd;
real value;
vsource #(.type("sine"), .ampl(3m), .phase(0), .freq(60M)) v1 (in,gnd);
oscillator #(.test_frequency(60M) , .amplifier_gain(15)) osc1(out,in);
endmodule

Hello Mr.Coram,
                      Thanks a lot for your response. I have run the tests for the situations that you have indicated and I notice extremely surprising results. I will attempt to answer the points you have put up and give you a general conclusion of my readings from the experiment.

I don't understand a couple things:
1) the mixer adds its inputs
A: I was not able to run it with difference, so for a first dry run, I just assumed everything was in phase and mixer would just add the input with the fedback signal. The amplifier would again just amplify in phase and the feedback would take a part out in phase. Hence I let mixer add its inputs.

2) the phase shifter sets flag1=0 @initial_step, but then immediately sets it to 1.
A: I am sorry. That part was just used for testing. I wanted to test driving the initial output of phase shifter to 0 and then check the result. I have rerun the whole code with just the line V(out) <+ beta * V(in);

Here are the two scenarios for which I have re run the simulations and the results enclosed.

case 1: Vout <+ Vin * beta;
Results :  V(in) the input source is out of phase with all the three remaining nodes. Vref (input to amplifier), Vout( output) and Vx(output of phase shifter) are all in phase with each other but 180 out of phase with vin. This really beats me.
Further all the signals are non zero sine waves. All are constant sine waves and not increasing sine waves as they ought to be. the amplitude relations are correct. Amp(vref) = Amp(vin) + Amp(Vx).  Amp(vout) = 15* amp(vref) and amp(vx) = 0.1 v(out).

case 2: Vout <+ vin*beta; and mixer has just the outside input and the phase shifter input is disabled.
results : All the signals are now in phase. !!!! Now why does it go out of phase in the earlier case???
         The amplitude relations are right again. vout = 15 vref.  vref = vin,   vx= 0.1vout.
         The signals are all constant sine waves.(this is to be expected).

Ideally, the results should be
1. All signals in phase.
2. All amplitude relations shd be the same.
3. All signals other than vin should be increasing sine waves (amplitude increasing in each cyle).
The third condition never seems to be happening.

please give me your thoughts/suggestions. I have been stuck with this for the last one week  :(
thanks a ton for the help.
aravind
Can you plot the "vx" voltage (the phase shifter output)? Does it become non-zero?
Supposing it is non-zero, is the mixer not adding properly?

If you drive the mixer's in2 port with a constant v-source (leaving the phase shifter's output hanging), does this change the answers above?

Thanks a lot Mr.Coram. I have noticed my mistakes with respect to phase. I just have one problem at this stage.

                 Because of the analog block, the three blocks , mixer (just a simple subtractor like i have it defined), the amplifier and phase shifter, operate concurrently.
                 If I want to have a sine wave of increasing amplitude, then all these things should happen sequentially. That is an amplifier should amplify the sine wave of the previous cycle and only then will i get an increasing sine wave.  Only then will my values for the amplifier gain and the feedback factor beta, affect the nature of the output. Ideally it shd be a constant sine wave when Amp * beta =1. else it shd be either an increasing or decreasing sine wave.Is there any way that I can do this in Verilog ams?

              Thanks again for all the wonderful insight. Please do reply if you have any ideas for this last question from me.
Thanks
aravind

There are probably several ways to get an increasing sine wave ... you could set up something where the gain of an amplifier is controlled by the RMS average of its input.  You could use absdelay() to delay the output of one of the blocks, though I'm not a big fan of the absdelay() operator.  But you have to decide for yourself what's the best way to model it.

Hello Mr.coram,
               Thanks a lot for your help. You are proving to be a godsend for me. The idea of trying to delay the waves by using the absdelay operator did occur to me. I included it as a part of the phase shift block and I was getting a run time error saying some small signal problem. Today after your advice on absdelay operator, I included the delay block after the phase shifter and I did get exactly what I was looking for. Now the oscillator is a function of Amp and beta. Thanks a lot. You rock.
Aravind
Geoffrey_Coram wrote on Jan 10^th, 2006, 10:47am: