Hi,
I am trying to write a verilog-A model for a circuit that will sense ‘a’ crossing below -17.99V and wait for 4us before the state changes from alive to dead. If it  goes above -17.99V before the 4us the state should get restored to alive. If there is a glitch, it should again wait for 4us after the glitch goes away.

  I am pasting the testcase.va file below:
////////////////////////////////////////////////////////////////////////////////
//////////////////////

`include "discipline.h"
module testcase(a,b,c,d,e,f,dummy);
inout a,b,c,d,e,f,dummy;
electrical a,b,c,d,e,f,dummy;
real state,state2;
branch(b,c) device;
parameter real kill_start = 0.0;
parameter real alive = 1.0;
parameter real kill_end = 2.0 ;
parameter real dead =  3.0;
analog begin

 @(initial_step) begin
     state = alive;  //alive state initially
     state2 = alive;
 end

 V(dummy) <+ 0;

  @(cross(V(a)+17.99,-1))  begin
     state = kill_start; //Start of kill
  end

  if(state == kill_start) begin
  V(dummy) <+ transition(2,4u);  //4us is the minimum kill pulse width required
  end


  @(cross(V(a)+17.99,1)) begin
      state2 = kill_end;
  end


  if((state == kill_start) && (V(dummy) >= 2)) begin  //flip the state to dead
   state = dead;
   end

  if((state == kill_start) && (state2 == kill_end)) begin  //insufficient pulse width.flip the state back to alive
   state = alive;
   V(dummy) <+ transition(0,0u);
   end

   if(state == dead)  begin
      I(device) <+ (V(b)-V(c))/3185.558 + V(a)*(V(b)-V(c))*0.000095016666667;
   end

   if(state == alive) begin
     I(device) <+ 0.00;
   end


end
endmodule

////////////////////////////////////////////////////////////////////////////////


I am pasting the testcase.sp file below:
**********************************************
*
*.param HSIMVERILOGA="testcase.va"
.verilog testcase.va

vsource a gnd pwl(0u 0      1u 0      2u 1.1v  5u 1.1v    6u -18v   15u -18v    16u 0v    17u 1.1v    18u 1.1v    19u 5v )
Vsd e gnd  pwl(0u 1.2v   1u 1.2v   2u 1.2v  5u 1.2v    6u  1.5v  15u  1.5v   15.5u 1.2v)
Vss d gnd  pwl(0u 0      1u 0      2u 0     5u 0       6u  1.5v  15u  1.5v   15.5u 0v)
Vfc0 b gnd pwl(0u 0      1u 0      2u 0     5u 0       6u  1.5v  15u  1.5v   15.5u 0v)
Vfc1 c gnd pwl(0u 1.2v   1u 1.2v   2u 1.2v  5u 1.2v    6u  1.5v  15u  1.5v   15.5u 1.2v)
Vpw f gnd pwl(0u 1.2v   1u 1.2v   2u 1.2v  5u 1.2v    6u  1.5v  15u  1.5v   15.5u 1.2v)
vgnd gnd 0 0

.model testcase macro language=veriloga
y1 testcase a b c d e f dummy
*** Simulation Time
.tran 10n 60u

.plot TRAN v(*)
.plot TRAN i(*)
*.print v(*)
*.print i(*)
.end
****************************************************

I am simulating it on eldo. I am getting the following error:
'testcase.va', line 29: Error : Cannot use analog operators or analog event (@) statements inside if or analog event (@) blocks with non-constant conditions.

'testcase.va', line 43: Error : Cannot use analog operators or analog event (@) statements inside if or analog event (@) blocks with non-constant conditions.

testcase.va: module(s)   testcase  Failed With Errors.

ERROR 1102: VERILOG_A :COMPILER doesn't run successfully, "compiler error with "testcase.va" . stop"



Can someone help me in solving this?

Thanks,

Rudy

You might be able to get the behavior you describe by taking full advantage of the transition function as follows ...
Code:

@(cross(V(a)+17.99))
    ;
eventual_state = (V(a) > -17.99) ? alive : dead;
state = transition(eventual_state, 4u, 0); 

state will transition to the desired value only after eventual_state has been stable for 4us.

-Ken