irfan
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Hi all!
I have a working Verilog-A model of this block and am now trying to model it in mixed-mode, i.e. Verilog-AMS. That is where I am having issues now: the out put simply keeps integrating up! This design is not exactly like the conventional dual-slope integrator, but very close.
As I don't have a picture handy, let me try to describe the behavior in one period, T:
@(posedge RESET) ----> Vout = 0.4 @(posedge UP)---------> Vout = Integration up of (V1+0.4) @(posedge SAMPLE) --> Vout = (max integrated voltage - 0.4V) @(posedge DN)------ --> Vout = integration down of (V2 + max value)
T = [RESET + UP + SAMPLE + DN],
Where, RESET = 0.08*T; UP = 0.42T; SAMPLE = 0.08*T & DN = 0.42*T
V1 & V2 are two different voltage sources.
In my analog model I am NOT modeling the RESET & SAMPLE portions as 8% of T. Instead, I am giving the integrator a very small time and a very small value to integrate. Perhaps that's why that model works and not this one?
Any feedback and comments will be most appreciated. If the above is not clear, I will post a diagram tomorrow morning.
Thanks,
Irfan
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