gitarrelieber
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Villach
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Here is also a code example for PRBS generator.
// VerilogA for wk_hu, prbs_gen, veriloga
`include "constants.vams" `include "disciplines.vams"
module prbs_gen(clkp, clkn, outx, outb); input clkp, clkn; output outx, outb; voltage clkp, clkn, outx, outb; parameter integer bit_num = 8 from [2:32]; parameter integer seed = 1 from [1:inf];
integer x, a1, a2, a3, a4, b, mask; analog begin @(initial_step) begin case (1) (bit_num == 2): begin a1=0; a2= 1; a3= 0; a4= 0; end // 2 [0,1] (bit_num == 3): begin a1=0; a2= 2; a3= 0; a4= 0; end // 3 [0,2] (bit_num == 4): begin a1=0; a2= 3; a3= 0; a4= 0; end // 4 [0,3] (bit_num == 5): begin a1=1; a2= 4; a3= 0; a4= 0; end // 5 [1,4] (bit_num == 6): begin a1=0; a2= 5; a3= 0; a4= 0; end // 6 [0,5] (bit_num == 7): begin a1=0; a2= 6; a3= 0; a4= 0; end // 7 [0,6] (bit_num == 8): begin a1=1; a2= 2; a3= 3; a4= 7; end // 8 [1,2,3,7] (bit_num == 9): begin a1=3; a2= 8; a3= 0; a4= 0; end // 9 [3,8] (bit_num == 10): begin a1=2; a2= 9; a3= 0; a4= 0; end //10 [2,9] (bit_num == 11): begin a1=1; a2=10; a3= 0; a4= 0; end //11 [1,10] (bit_num == 12): begin a1=0; a2= 3; a3= 5; a4=11; end //12 [0,3,5,11] (bit_num == 13): begin a1=0; a2= 2; a3= 3; a4=12; end //13 [0,2,3,12] (bit_num == 14): begin a1=0; a2= 2; a3= 4; a4=13; end //14 [0,2,4,13] (bit_num == 15): begin a1=0; a2=14; a3= 0; a4= 0; end //15 [0,14] (bit_num == 16): begin a1=1; a2= 2; a3= 4; a4=15; end //16 [1,2,4,15] (bit_num == 17): begin a1=2; a2=16; a3= 0; a4= 0; end //17 [2,16] (bit_num == 18): begin a1=6; a2=17; a3= 0; a4= 0; end //18 [6,17] (bit_num == 19): begin a1=0; a2= 1; a3= 4; a4=18; end //19 [0,1,4,18] (bit_num == 20): begin a1=2; a2=19; a3= 0; a4= 0; end //20 [2,19] (bit_num == 21): begin a1=1; a2=20; a3= 0; a4= 0; end //21 [1,20] (bit_num == 22): begin a1=0; a2=21; a3= 0; a4= 0; end //22 [0,21] (bit_num == 23): begin a1=4; a2=22; a3= 0; a4= 0; end //23 [4,22] (bit_num == 24): begin a1=0; a2= 2; a3= 3; a4=23; end //24 [0,2,3,23] (bit_num == 25): begin a1=7; a2=25; a3= 0; a4= 0; end //25 [7,25] (bit_num == 26): begin a1=0; a2= 1; a3= 5; a4=25; end //26 [0,1,5,25] (bit_num == 27): begin a1=0; a2= 1; a3= 4; a4=26; end //27 [0,1,4,26] (bit_num == 28): begin a1=2; a2=27; a3= 0; a4= 0; end //28 [2,27] (bit_num == 29): begin a1=1; a2=28; a3= 0; a4= 0; end //29 [1,28] (bit_num == 30): begin a1=0; a2= 3; a3= 5; a4=29; end //30 [0,3,5,29] (bit_num == 31): begin a1=2; a2=30; a3= 0; a4= 0; end //31 [2,30] (bit_num == 32): begin a1=1; a2= 5; a3= 6; a4=31; end //32 [1,5,6,31] default $strobe("Error. Should never get here."); endcase mask = pow(2, bit_num) -1; x = seed; x = x & mask; //mask the unavailable bit; end @(cross(V(clkp, clkn), +1, 10p)) begin b = ((x>>a1)^(x>>a2)^(x>>a3)^(x>>a4))%2; x = ((x<<1) & (mask-1)) + b; end V(outx) <+ x; V(outb) <+ b; end
endmodule
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