Hi vhdl00,

regarding your problems I may want to follow the guidelines:

1) The voltage at the drain of M6 and M7 (node called (9) in your schematic) is defined by the output voltage (10) scaled down by the Vsg of M8. Therefore you can grant the saturation of both M6 and M7 by choosing a proper output common mode and the current/size of M8. You should also grant a very strong saturation since the opamp's output swing also affect the biasing point of node (9).
If your specifications claim for large output common-mode compliance and/or verly large output swing, you may introduce some biasing control-loop. Please note that in many applications the output common mode of your opamp is fixed by external factors and, once knonw, a proper biasing can be settled without additional extra servo-loops.

2) It seems to me that your current mirrors suffer from channel-lenght modulation: if the drain-to-source voltage of the devices is different, short channel effects may introduce a "copiature" error. This can be attenuated by longer channel devices and/or cascoding.

I hope this could be useful, regards.
Cri

Cri Azzolini and Huber, thanks a lot for you guys replies.

I was alway thinking the simulations was ideal---there should be no offset at all, seems I am wrong at this point. .
I thought dc gain measured in closed loop just to consider the loading effect. but in switched capacitor configuration, just like open circuit, am i right?
thanks again

Hi All,

I realized that this topic was somehow related to my current problem. In the telescopic opamp design, I had difficulties in getting the all transistors in saturation within certain region. I am wondering the comment that "the DC operation point should be simulated in close-loop" also can be applied to differential amplifier.

Thanks in advance,
Steven

Hi Cri,

         thanks for your inputs.

         Now I have some doubts for the design medthodology. I thought working in a bottom to top way, We need design and test a single design module and build them up. But seems you are suggesting to hook up all the components together at the beginning and do the simulations.

         Steve also mention the small deviation margins for some devices, you meam with CMFB setting the operating points, they are not issues anymore, right?

     


     

Steven,

for your simulation with Spice I suggest you to perform DC biasing using an ideal continuous-time CMFB: you may use voltage-controlled-voltage-sources and so on. The results can be a little bit affected by this substitution but it is a starting point; unfortunately with this approach you can not verify the stability of the CMFB loop: in my opinion this is the main problem of this simulation test-bench.
Once your opamp is biased, you should swap back to the switched-capacitors CMFB and perform transient analysis in order to fix the last details of the CMFB block.

Regarding your question about the DC-gain of telescopic amplifiers, you know, it is related to the transconductance of the input devices and to the small-signal resistance seen at the output nodes: if you do not want to raise your tail power consumption, you may try to insert boosting servo-amplifiers for both cascoded devices and active load. This solution is quite diffused in literature and can greatly improve the output resistance but it is quite tricky for high-speed opamps since boosting amplifiers can slow down the step response. If you are interested you may consult the paper:
D.Vecchi, C.Azzolini, A.Boni, F.Chaaoub, L.Crespi, "100-MS/s,14-b Track-and-Hold Amplifier in 0.18-um CMOS", Proc. of 2005 IEEE ESSCIRC Conference.
or contact me by email.
Finally, do not forget the DC-gain is also limited by the voltage output swing (which can drive the output devices in triode region) and, last but not least, by the technology you are using!

Bye,
Cri