Hi,

I've created a module Atemp(), and am trying to instantiate ten instances of Atemp. Here is how the book says it should be done:

Atemp tempArray[0:9] ();

The error that I get:
line 136: "Atemp tempArray[<<--? 0:9] ();
line 136: Error: syntax Error

I have tried this and many other permutations (Atemp tempArray [0:9] ();  Atemp [0:9] tempArray ();  Atemp tempArray[0:9]();  ...etc) in the off chance that that would be it, to no avail.

All lines around this error line are fine, there are no other errors. After browsing through the FAQ's here, as well as consulting the book, I seem to be at a dead end for now. I would appreciate your input as to how this syntax should be.

Thanks,
Xter

Hello,

Thanks for replying.  

>>That syntax looks OK per the Verilog-AMS LRM, but I don't see any examples in the LRM that actually use the range ([0:9]).
...
>>I also don't see the LRM talking about how to connect to the array of instances, eg if you had a 10-wide bus and you wanted to connect bus[0] to tempArray[0], ...)

I was referring to an example in the Designers Guide to Verilog AMS, page 229, the example is for multiple instantiations. That example instantiates eight resistors in an array, "resistor #(50) r[1:8] (bus,gnd)", where bus is an array of 8, bus[1:8]. I was hoping to use the same syntax to instantiate one of my own modules.

>>(I"m curious why you want 10 instances of something with no connections;
The module Atemp was just a dummy module to get the syntax right. In actuality, I am building a flash ADC module, and am creating smaller modules, such as preamplifiers. Instead of manually instantiating thirty-three preamplifiers , I would like to just instantiate an array of preamplifiers whose inputs and outputs are busses. This will allow me to easily access any of the preamplifiers by index, instead of manually calling up preamps.

If instantiating an array of modules does not work, I would appreciate it if you could point out another way of easily accessing a large number of instances of the same module without doing it manually.

Also, I am currently using Verilog-A, it is possible that the creating an array of modules is an AMS feature. I will double check this. Thanks.

-Xter