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The Designer's Guide Community Forum › Design Languages › VHDL-AMS › Cascading different sample rate blocks in VHDL-AMS
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Cascading different sample rate blocks in VHDL-AMS (Read 35 times)
Visjnoe
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Cascading different sample rate blocks in VHDL-AMS
Jan 21st, 2006, 2:44am  

Hello,

anyone ever modeled a cascade of mixed-signal blocks with different sample rates in VHDL-AMS?
More precisely, a comb filter @2*Fs followed by a SC biquad @Fs with Fs the sample rate...

Did this pose any problems?

Kind Regards

Peter
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