Hi Neoflash,

I guess you are talking about digital error correction. You can find quite some interesting documentation by googling for this term. A brief description is given here:
http://www.maxim-ic.com.cn/appnotes.cfm/appnote_number/1023/ln/cn
http://www.ee.oulu.fi/~timor/EC_course/chp_5.pdf
The basic idea is that each stage (except the last) generates an additional bit compared to the corresponding residue gain of the stage. If you multiply the residue by 4, the stage generates 3 bits. In this way, you extend the full-scale of each stage and avoid the amplified residue to exceed this same full-scale (not so easy to explain with words). Jespers also has a nice extensive description of this in his book "Integrated Converters : D to A and A to D Architectures, Analysis and Simulation".

Paul

Hi Neoflash,

You have provided part of the answer yourself:

From 1.5Bit stage, we got two bits. I think they are all useful. We should use digital logic to compute final results from both of them. So, it is not really redundant, right?  

You get 2 bits from each 1.5-bit stage. Redundancy does not mean that you don't need both the bits. It just means
that the 2 bits do not really contain a full 2 bits of information. For instance, the output of a 1.5-bit stage is 00,01,10
but never 11. Therefore, there is some redundancy. There are various ways of looking at this redundancy, but hopefully, this is
enough.

Secondly, when you add the bits, you can see that you implement only a gain of 2 (1 bit shift). If you had no redundancy,
then you would shift the outputs of each stage by 2 positions, which would mean that there would be no overlap between
outputs from 2 different stages.

On missing codes, I would say that the digital redundancy helps in removing missing levels and not missing codes. Essentially,
you implement only a gain of 2 in your MDAC while using more comparators than would be needed, thus creating more decision levels
(redundancy).

On the analog side, this is equivalent to implementing a gain of 2 in the MDAC while using 2 comparators instead of 1. You should
look at the residue transfer curve of the MDAC. You will see that the residue level around the comparator thresholds is limited to
half of the full scale range. Therefore, any comparator offset can push the residue curve up/down by a quarter of the full scale range (VREF/4)
without causing missing levels in the later stages.

I guess it is best if you read up some references. Here is a paper, but first look at the references section at the paper by Lewis [7].
This paper by Lewis is one of the early ones on digital redundancy, and if it does not explain the concept completely well to you,
then look at Cline's thesis (kabuki.eecs.berkeley.edu). Hopefully, these help.

Regards
Vivek

vivkr wrote on Feb 1^st, 2006, 12:27am:


I agree with your opinion on this part absolutely. That's against what I read in lecture notes from EE246 UCB, however, I believe we are right.