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rhys_williams

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Is the worst-power corner really worst power?
Feb 02^nd, 2006, 7:36am

I've been simulating a circuit over all possible combinations of:

nominal, fast, slow device models
VDD = 3.0, 3.3, 3.6 V
temp = 0, 27, 125 degrees

Many sources refer to the worst power corner as fast/3.6/0 degrees (for instance Weste & Eshraghian). In the circuit I'm looking at (a current-steering DAC), this corner actually consumes slightly less than the nominal/3.3/27 run. The worst power consumption occurs at slow/3.6/125.

Any idea what's going on here?

The only thing I can think of is that worst-power or worst-speed corners really apply only to circuits comprised mainly of CMOS gates. My DAC consists mainly of an array of current sources, which consume 20mA at all times.

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vivkr

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Re: Is the worst-power corner really worst power?
Reply #1 - Feb 3^rd, 2006, 12:13am

Hi,

The worst-power corner should usually also depend strongly on the kind of circuit you use.
In any case, I think even for digital circuits (the ones largely discussed in the book you mention)
should probably show more power consumption at high temperature rather than low temperature
for the following reasons:

1. The threshold voltage of MOS transistors falls with rising temperature.

2. The junction leakage increases (not visible if your circuit itself has a large static power consumption to start with).

3. The transitions get slower since the mobility of the channel drops off. Therefore, the switching duration increases,
allowing for crowbar current to flow between VDD & VSS for a longer while. Note that the falling mobility should counter the falling
VT to some extent as the current Ids = Kn(W/L)(Vgs-Vtn)^2 (not correct to assume saturation throughout but for simplification).

Regards
Vivek

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vivkr

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Posts: 780

Re: Is the worst-power corner really worst power?
Reply #2 - Feb 3^rd, 2006, 12:57am

Hi,

The worst-power corner should usually also depend strongly on the kind of circuit you use.
In any case, I think even for digital circuits (the ones largely discussed in the book you mention)
should probably show more power consumption at high temperature rather than low temperature
for the following reasons:

1. The threshold voltage of MOS transistors falls with rising temperature.

2. The junction leakage increases (not visible if your circuit itself has a large static power consumption to start with).

3. The transitions get slower since the mobility of the channel drops off. Therefore, the switching duration increases,
allowing for crowbar current to flow between VDD & VSS for a longer while. Note that the falling mobility should counter the falling
VT to some extent as the current Ids = Kn(W/L)(Vgs-Vtn)^2 (not correct to assume saturation throughout but for simplification).

Regards
Vivek

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