I've been simulating a circuit over all possible combinations of:
- nominal, fast, slow device models
- VDD = 3.0, 3.3, 3.6 V
- temp = 0, 27, 125 degrees
Many sources refer to the worst power corner as fast/3.6/0 degrees (for instance Weste & Eshraghian). In the circuit I'm looking at (a current-steering DAC), this corner actually consumes slightly less than the nominal/3.3/27 run. The worst power consumption occurs at slow/3.6/125.
Any idea what's going on here?
The only thing I can think of is that worst-power or worst-speed corners really apply only to circuits comprised mainly of CMOS gates. My DAC consists mainly of an array of current sources, which consume 20mA at all times.