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steven

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Comparator resolution
Feb 08^th, 2006, 6:46pm

Hi,

I have a question on comparator's resolution. The comparator resolution is related to the offset voltage. Without offset compensation, the offset voltage is proportional to Vt variance and proportional to Vov. With offset compensation, the offset voltage can be further reduced. In both of these two cases, how to justify the comparator resolution due to fabrication process variances such as Vt? Or is it simply not possible without actual measurements?

Thanks,
Steven

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huber

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Re: Comparator resolution
Reply #1 - Feb 10^th, 2006, 8:53am

The main source of comparator offset is threshold voltage mismatch, but dynamic issues (such as mismatch in load capacitance) tend to result in larger offsets than you would expect. There was a paper presented on Tuesday at ISSCC that implemented tunable load capacitance to compensate for comparator offset; very cool stuff. If you have good mismatch data then you should be able to simulate comparator mismatch accurately. Not sure what you mean by "how to justify the comparator resolution".
-Dan

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steven

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Re: Comparator resolution
Reply #2 - Feb 17^th, 2006, 12:25pm

huber wrote on Feb 10^th, 2006, 8:53am:

If you have good mismatch data then you should be able to simulate comparator mismatch accurately. Not sure what you mean by "how to justify the comparator resolution".
-Dan

Hi Dan,

Ok, I see. When I said "how to justify the comparator resolution", I was thinking to justify the resolution analytically rather than simulation or measurement.

Thanks for clearing up.
Steven

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sugar Community Member Offline Posts: 54	Re: Comparator resolution Reply #3 - Feb 19^th, 2006, 8:21pm huber wrote on Feb 10^th, 2006, 8:53am: There was a paper presented on Tuesday at ISSCC that implemented tunable load capacitance to compensate for comparator offset; very cool stuff. -Dan hi, huber will you please tell me the title of the paper, I am really interested in it. thanks in advance. river
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huber

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Re: Comparator resolution
Reply #4 - Feb 20^th, 2006, 10:26am

Hi river-

The paper was presented in Session 31: Very High Speed ADCs and DACs. The title is "A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process". The authors are G. Van der Plas, S. Decoutere, and S. Donnay. Unfortunately I don't think the 2006 proceedings are online yet, so you'll either have to wait or find someone with a paper copy. Basically they used a sense-amp-sytle latch loaded with banks of PMOS gate caps. Each cap has a source/drain terminal that is controlled by a programming bit, which determines if the cap has an inversion layer or not.

-Dan

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