vivkr
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" I finally get the simulation correct. It is true that the bipolar pair has better matching, but the offset of CMOS diff pair can be small (about +- 600uV) also by using multiple large input transistors. However, I am not sure whether the result is a simulation artifacts or not. "
If you are doing Monte Carlo simulations, then it is no coincidence that the offset of the CMOS opamp goes down with large input devices.
The random mismatch of matched circuit elements typically goes down as 1/sqrt(Area). However, as mentioned in other posts here, the mismatch of MOS devices is an extremely sensitive function of various factors, most importantly the gate overdrive. This is primarily due to the dominance of VT mismatch in MOS devices, and the fact that large VGS reduces the effect of this mismatch. You can derive this yourself by analyzing sensitivity of IDS with respect to VT or look it up in Razavior Gray & Meyer.
More information can be found in several papers and texts, and also your process docs on mismatch, and techniques for mismatch reduction are also discussed on Bob Pease's homepage and his articles.
One very good paper on MOS mismatch is:
Patrick G. Drennan, Colin McAndrew, "Understanding MOSFET Mismatch for Analog Design," IEEE JSSC, March 2003 pp. 450-456.
The above gives a clear and balanced treatment of the subject. Above all, remember that Monte Carlo assumes "well-matched" devices. Therefore, make sure your layout is well-matched and not susceptible to systematic drift by using common-centroid techniques.
Regards Vivek
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