Hi all,

I am currently designing using bicmos technology but I am totally unfamiliar with bipolar transistors. I have been reading articles regarding the fact that bipolar OPAMP have a very good matching and give better performance in term of offset voltage compared to CMOS. In order to test it out, I designed 2 OPAMPs, 1 with bipolar and 1 with CMOS differential pair, and hook them up in non-inverting unity gain feedback configuration, and measuring the offset by comparing the voltage on non-inverting input and output. I ran a 100 points monte carlo with mismatch and the output result surprised me. For CMOS, the offset I get is about +-800uV max. But for bipolar result is about +- 1.5mV max. After tweaking the devices, the offset for bipolar finally goes down to about +- 500uV, although smaller than CMOS, but is not what I am expecting. I wonder why this is happening, it is because I am using CMOS current mirror? or CMOS process becomes better that they actually have matching close to bipolar process? Or is the measurement is wrong? Please advice.

in bipolar process all "active" parts of a pnp transistor are created in one processing step, with one mask. So called "base" p-diffusion produces both the emitter and collector inside the N-tub and defines the base at the same time. I think a bicmos PNP is similar to the bipolar one in this. That is one-mask operation for the whole transistor. A MOS
transistor is a product of a more complex operation .. even small mask misalignments may result in Gm variation.
PNP input diff pair is often favoured where the low voltage offset is the concern i.e. precise voltage regulators.
Does this answer your question?

" I finally get the simulation correct. It is true that the bipolar pair has better matching, but the offset of CMOS diff pair can be small (about +- 600uV) also by using multiple large input transistors. However, I am not sure whether the result is a simulation artifacts or not.  "

If you are doing Monte Carlo simulations, then it is no coincidence that the offset of the CMOS opamp goes down with large input devices.

The random mismatch of matched circuit elements typically goes down as 1/sqrt(Area). However, as mentioned in other posts here, the mismatch
of MOS devices is an extremely sensitive function of various factors, most importantly the gate overdrive. This is primarily due to the dominance
of VT mismatch in MOS devices, and the fact that large VGS reduces the effect of this mismatch. You can derive this yourself by analyzing sensitivity of IDS with respect to VT or look it up in Razavior Gray & Meyer.

More information can be found in several papers and texts, and also your process docs on mismatch, and techniques for mismatch
reduction are also discussed on Bob Pease's homepage and his articles.

One very good paper on MOS mismatch is:

Patrick G. Drennan, Colin McAndrew, "Understanding MOSFET Mismatch for Analog Design," IEEE JSSC,  March 2003 pp. 450-456.

The above gives a clear and balanced treatment of the subject. Above all, remember that Monte Carlo assumes "well-matched" devices. Therefore,
make sure your layout is well-matched and not susceptible to systematic drift by using common-centroid techniques.

Regards
Vivek

vivek - I poked around on Pease's web page (great page - glad he's finally online!).  Anyway, I couldn't find the stuff on mismatch.  Do you have a specific link?

vivkr wrote on Mar 15^th, 2006, 12:32am: