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sugar Community Member Offline Posts: 54	how to simulate stability of PLL Mar 02^nd, 2006, 3:30am can we do transistor level stability simulation of a PLL circuit in spectre? how?
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Eugene

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Re: how to simulate stability of PLL
Reply #1 - Mar 2^nd, 2006, 8:25am

The conventional method of analyzing the stability of a pll involves a phase domain model. To analyze the device level model directly, you are constrained to the voltage domain. If you could get an RF simulator to converge on the correct periodic steady state solution, you MIGHT be able to compute the frequency response of the loop gain. I have always wanted to try something similar with switch mode power supplies. The pll presents a harder problem because of the VCO. An alternative is to study step responses with transient analyses. Aside from those two approaches, I don't know of any way to do a stability analysis directly on a transistor level model. I'd be very interested if anyone else knows of one.

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sugar

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Re: how to simulate stability of PLL
Reply #2 - Mar 2^nd, 2006, 5:45pm

Eugene,

By modeling pll in phase domain, we can analyze its stability.
But this method is error-prone and also difficult to model the parasitic effect.
I remember Andrew mentioned pstb somewhere, is it the one we are looking for?

Transient analysis is helpful but through transient analysis we can not know
how much margin there is and maybe for step response it's stable but for some
other stimulus it's unstable.

By the way, can we insert a AC voltage source between LPF and VCO to break the
loop to do the stability analysis? because at this node, the signal is voltage
rather than phase.

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Eugene

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Re: how to simulate stability of PLL
Reply #3 - Mar 3^rd, 2006, 2:14pm

Quote:

By modeling pll in phase domain, we can analyze its stability.
But this method is error-prone and also difficult to model the parasitic effect.
I remember Andrew mentioned pstb somewhere, is it the one we are looking for?

I don't have access to pstb yet but if it's what I think it is (phase/gain margin after a pss anaylysis) then yes, that's what I was referring to.

Quote:

Transient analysis is helpful but through transient analysis we can not know
how much margin there is and maybe for step response it's stable but for some
other stimulus it's unstable.

Usuallly, if the system is marginally stable the step response rings a long time. You would have to have some sort of unobervable unstable state for the step response not to show it and if you did have one, the loop gain could miss it as well. As long as the step has a sharp enough rise, it should excite any observable unstable state. The only time I've seen the stimulus make a difference is when the instability depended on the size of the disturbance. In that case, the AC analysis will be less reliable than the transient analysis.

Quote:

By the way, can we insert a AC voltage source between LPF and VCO to break the �
loop to do the stability analysis? because at this node, the signal is voltage �
rather than phase.

I agree: the node between the LPF and VCO is a convenient place to insert the AC source for a phase domain model or a pstb approach with a voltage domain model.

-Jess

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Geert New Member Offline Posts: 2 Delft, The Netherlands	Re: how to simulate stability of PLL Reply #4 - Mar 6^th, 2006, 4:06am In general a transient run takes a long time to simulate, since the reference frequency and VCO frequency are not in the same range. However when you scale the frequency of the VCO, the KVCO and the N-divider ratio you can simulate in transient "quick".
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