need  help  regarding variation of bandgap output voltage:

Process used: standard CMOS,
BJT device: parasitic vertical, ratio=12:2
architecture: bandgap with opamp, opamp gain ~ 40dB, loop AC stable
measurement result: +/-70mV standard deviation, mean-value=1.2V @room temperature,
question:
   need help / reference material  for a systematic method to reduce with the variation,
I wonder if the major variation come from the BJT process control??
Does someone has experience upon this?

Hi,

you give a standard deviation of ±70mV on Vbg, but you don't say what is the number of measurements and especially what is the variable.
Are there several measurements on the same die in a timely manner, in which case the reason would be noise/drift?
Are the measurements performed on different dies, in which case the problem is process variations (device mismatch, opamp gain and offset, ...)
Are the measurements performed while sweeping temperature, in which case your variations are due to the higher temperature coefficients and opamp gain and offset variations?

In any case 40dB of DC gain in the opamp seems low to me as already stated by chase. You can also expect the DC gain to change a little over temperature.

Based your answers to the above questions it should be possible to give further indications on the possible sources.

Paul

Dear Sir:

Allow me to answer Paul first: It's the second case:
"the measurements performed on different dies, in which case the problem is process variations (device mismatch, opamp gain and offset, ...)"
upon 100 samples at room temperature.

Secondly, please refer to the attachment:
The gain is not that high, and what we have for comparator input stage is W/L=10u/10u m=8 pmos pair.
I'll be back with some monte carlo analysis results.

Thanks in advance,

Dear Raul:

Those data of chip to chip variation are obtained at same VDD.

I could not understand why this variation has something to do with PSRR.

Thanks