need help regarding variation of bandgap output voltage:
Process used: standard CMOS,
BJT device: parasitic vertical, ratio=12:2
architecture: bandgap with opamp, opamp gain ~ 40dB, loop AC stable
measurement result: +/-70mV standard deviation, mean-value=1.2V @room temperature,
question:
need help / reference material for a systematic method to reduce with the variation,
I wonder if the major variation come from the BJT process control??
Does someone has experience upon this?