With respect to the post http://www.designers-guide.org/Forum/YaBB.pl?num=1142343700 I would like to know how to best dither a FM signal in VerilogA/AMS. So far I can only think of creating multiple delayed instances of the FM signal and then randomly selecting one tap with a mux.

1) ___|^-----|_____|^-----|____|^---|
2) __|^-----|_____|^-----|____|^---|
3) ____|^-----|_____|^-----|____|^---|
4) |^-----|_____|^-----|____|^---|

Essentially, the positive edges of the FM signal will phase shift randomly.

In VerilogA/AMS I tried using a absdelay() with a random shift generated using $rdist_uniform but when doing so the simulation will terminate saying that the delay has changed. Is a variable delay possible in VerilogA/AMS?

Are there any other ways to obtain a dithered FM signal?

Regards,
Sven

You can also find it in http://www.designers-guide.org/VerilogAMS/functional-blocks/osc/osc.va. You would use the oscillator with accumulating (or FM) jitter.

-Ken

Thanks for the response Ken. When using the VCO including jitter I can dither the FM signal.
When only the FM signal is available I ended up using transition(n ? 1 : 0, dT, tt);  where dT is created using $rdist_uniform. This works fine as a model but how would one implement this with real circuitry?

Thanks,

Ps. When looking at different examples from the Verilog-AMS section I noticed very different seed values for each application. Is there a reason for choosing the different seed values for different applicaitons or did you just pick a number?