sheldon
|
Vivkr,
Can't you auto-zero the comparator while sampling the input signal? You don't need to auto-zero the entire comparator, you only need to auto-zero the first few stages. Or you can ping-pong multiple ADCs, this is approach is used to build high speed pipeline ADC. BTW, here are a few papers on sub-radix 2 successive approximation ADC design.
Design and Modeling of a 16-bit 1.5MSPS Successive Approximation ADC with Non-binary Capacitor Array, GLSVLSI ’03, April 28-29, 2003,
A 12-bit ADC Successive-Approximation-Type with Digital Error Correction, Kanti Bacrania, JSSC, Dec. 1986
Best Regards,
Art Schaldenbrand
|