I am having a problem trying to simulate with a verilog-a file.  My steps where:

1. File->New->Create  VIEW Name: veriloga  TOOL: VerilogA-Editor
2. File->New->Create  VIEW Name: symbol   TOOL: Composer-Symbol

I edited the veriloga.va file and matched up the veriloga and symbol pins.  The syntax seems to be okay.

I created a Hierachy as follows:

Library list: ap_sim ap_lib
View List: spectre cmos_sch schematic veriloga ahdl
Stop List: spectre veriloga


The schematic simulates just fine until I use the hierachy editor to switch in a verilog view. After clicking Netlist and Run I get the error:

ERROR: Netlister: unable to descend into any of the views defined in the view list: "veriloga" for instance I14 in cell SigmaDelta_sim. Either add one of these views to: Library: ap_lib Cell: firstorder_sigmadelta or modify the view list to contain an existing view.

I have another verilog file form an old employee that I copied into my lib.  Removing my verilog symbol and placing in the that symbol causes no problem.  

My Setup simulator/dir/Host simulator is "Spectre"

Note:  I get the same problem if I remove a pin from the verilog code and symbol of the old cell.  It as if I need to compile / update the cell somehow.


Help Please

The VI editor normally comes up, but I use another editor, that doesn't give me an indication that it passed the parser.  I am now using the VI editor for all changes.  I now get the passed syntax (parser) check message.  Everything seems to be working fine now.  

Thanks for the help

Yes, the parser is invoked to ensure that the "cdb" file (or "oa" file if using OpenAccess) is created for the verilog-a view. This contains information about the terminals and directions, and allows the netlister to view switch into the verilog-a view. Editing the file outside of DFII doesn't create this additional file in the cellView, and so it doesn't know how to switch into the verilog-a view.

As Bernd said, editing from within DFII will trigger the parser when the editor exits.

Regards,

Andrew.