smlogan
Community Member
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Posts: 52
Boston, MA
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Dear ccd,
I've read over the many good responses. I've had the opportunity to simulate the impact of supply noise on many oscillator types. With respect to the ring based VCO, the sensitivity of the design to supply and ground noise is a function of the degree to which the propagation delay is dependent on the supply and ground levels. Since the parameters effecting the propagation delay may not be accurately represented in its small-signal model, as many have stated, the accuracy with which a small-signal analysis estimates the sensitivity of the design to the supply and ground modulation is limited. Hence, I would also recommend the use of large signal simulations to estimate output jitter sensitivity to supply and ground modulation.
As a means of more clearly examining the parameters responsible for the sensitivity, it might be worth examiningthe variation in propagation delay of the basic delay cell of the VCO. You might even start with a set of transient simulations where the DC value of VDD and GND are independently changed and compute the propagation delay time. By plotting the propagation delay as a function of VDD or GND, one may compare the propagation delay sensitivityof different topologies of delay cells. Of course, the freqeuncy of the modulation (and hence its non-DC nature) must still be considered. For example, on chip bypass capacitance will serve to attenuate the modulation on VDD and GND above a specific frequency. Nevertheless, the lower the sensitivity of the propagation delay is to the DC variation of VDD and GND, the more immune it will be as the frequency of the modulation is increased from DC.
Just thought I would add a few pennies to the discussion,
Shawn
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