can any one help??

or should I just build interpolator in to a symbol with verilog code and simulate with SpectreVerilog??

Hi Andrew~!!

Thanks for your kindly reply~!!

but, I still have some questions:

What is MMSIM60? is that means I can't read VCD format file in IC5141?
Sorry, I can't attache the file here, so I just put some rows...
00000000000000
00000011111100
00000111100000
00001010010101
00001100001010
00001100110011
00001100001101
00001010011011

I guess I will thry the $fopen()/$fscanf() to read the file...
(I thought verilogA does not contain fscanf?)

change the file to PWL seems too complecated...

Thank you~

Best regards,

YiLi

with IC5141 there is a library called bmslib
it has a few verilog-a models in it..
a helpful one in thls case is busset8 - to show you how to take integer -> 8 bits out..
(thats tested and what folowes isn't .
what you want to do is read the integer from the file then set 14 outputs based on that integer..

module file2source (out, clk, gnd);
output [13:0] out;
electrical [13:0] out;
input clk;
electrical clk;
inout gnd;
electrical gnd;

parameter vhi = 1.5;
parameter vlo = 0;
parameter tr = 20p;
parameter tf = 20p;
integer vd[26:0]; // number of samples to read from the file if doing it all at once?
integer vd; // holds the entire integer value if reading from the file until its empty
integer infile;

analog begin
 @(initial_step) begin
    infile = $fopen("file.dat", "r");
   $fscanf(infile, "%d", vd); // only reading 1 integer (integer has 32 bits)
 end
 @(cross(V(clk,gnd)-0.5*Vhi, 1)) begin // posedge
   $fscanf(infile, "%d", vd); // only reading 1 integer (integer has 32 bits)
  // what if EOF?
 end
 generate i (13, 0)  begin
   V(out[i],gnd) <+ transition((vd & 1<<i)?vhi: vlo, 0, tr, tf);    
 end

// note this form of generate statement is deprecated syntax.. but still works in 5141..
and mmsim6.. there is a newer form of the syntax in the AMS2.0 LRM, but last time I tried that
I think it didn't work in 5.0.33 (now in EOL - but I still have to support it for a while yet.. so I'm waiting a little longer
before going to the new syntax..  you may be luckier..

-------------------------------
OR you could run spectreVerilog
OR you could run AMS designer, and write your DAC to use Logic input values (some examples of that in bmslib too..
but AMSD takes 3 tokens..

G'luck!
jbd